1. FIELD OF THE INVENTION
The present invention relates to the field of static path analysis of digital circuits, and more particularly, to improved apparatus and methods for handling multi-cycle paths in simulation, static timing analysis and logic synthesis.
2. ART BACKGROUND
In designing a digital circuit, it is advantageous to conduct simulations with respect to timing analysis and logic synthesis prior to the finalization of the circuit design. Automated simulation and timing analysis programs have been developed to estimate circuit design performance prior to the fabrication of the digital circuit. For example, a program referred to as "MOTIVE".TM. has been developed by Quad Design Technology of Camarillo, Calif. to conduct timing analysis of proposed digital circuits. Logic synthesis programs often attempt to improve the performance of a circuit design. When so doing, they must consider whether one circuit to implement a given function is faster than another. Hence, they must contain a subprogram to perform timing analysis.
Generally, there are two kinds of logic simulation. The first type is that which is purely functional and is sometimes called "zero delay" or "unit delay", such that the exact timing of each gate within a digital circuit is not considered in the simulation. The other form of logic simulation involves the simulation of the delays of each logic gate, and the determination of when signals arrive at certain locations within the circuit. This second type of logic simulation is commonly known as "timing logic simulation". Timing logic simulation attempts to determine the slowest electrical paths in a digital circuit. A variety of patterns of zeros and ones are provided to the circuit for purposes of simulating data pattens which the circuit may encounter. The use of timing logic simulation requires a significant amount of program time, and it is possible that if a particular data pattern is inadvertently not tested, the worst path in terms of delay will not be detected.
Static path analysis was developed as an improvement to timing logic simulation, wherein all possibilities of data paths are evaluated in one static pass through the proposed circuit. An advantage of static path analysis is that numerous data patterns need not be inputted into the circuit. All circuitry comprising the circuit is divided into combinational logic, where the output is purely a function of the inputs at the moment (plus some delay time for the signal to be driven through the combinational logic), and sequential logic where some memory buffering may occur. The most efficient design of a circuit frequently requires the use of multi-cycle paths (MCPs) which comprise sections of combinational logic whose delay exceeds the relevant clock cycle time. However, static path analysis assumes that a signal will propagate from one sequential element to another within one cycle. Accordingly, static timing analysis is made more complicated by the existence of multi-cycle paths.
Current approaches to handling multi-cycle paths and static timing analysis programs are inadequate. For example, in one prior art method called "exception noting", the static path analysis program allows a circuit designer to notify the timing analysis software that a path (say from point A to point B) in a digital circuit is a multi-cycle path taking N cycles. It is necessary for the designer to identify each such multi-cycle path manually, and create a file listing all MCPs. This process is error prone, and may lead to an inaccurate static timing analysis if the designer claims that a path is multi-cycle, when it in fact is not. In addition, if a value from a multi-cycle path in a zero delay simulation is read before it is actually in a valid state, no error will be detected. Also, the exception noting approach does not assist logic synthesis software to determine which paths on a design are really time critical. For example, if the clock cycle is 25 nanoseconds, a single cycle path taking 30 nanoseconds is much more important to optimize than a two cycle path taking 40 nanoseconds, but there is no mechanism for the synthesis software to take this into account. The synthesis software will, therefore, attempt to bring both paths into conformance with the 25 nanosecond limit. The program "MOTIVE".TM. is of the type which requires exception noting for multi-cycle paths.
Another prior art method known as "latch insertion" eliminates multi-cycle paths from many circuits by physically adding digital "flip flops" to break the paths into single cycle segments. However, the addition of physical flip flops into the circuit to break the path up into single cycle segments adds additional cost and hardware size, and degrades performance since flip flops consume area and power, and have non-zero delay. In addition, they do not contribute any functionality to the circuit, and designers are very reluctant to insert them merely to assist a static path analysis program. However, the use of latch insertion does provide consistency among the simulation, timing analysis and logic synthesis of the design, since all of the programs currently in use are capable of recognizing the flip flops as valid circuit components.
As will be described, the present invention provides apparatus and methods to increase the performance of static path analysis by avoiding problems associated with multi-cycle paths in digital circuits. The present invention inserts conceptual devices referred to as "path breakers" into digital circuits to convert multi-cycle paths into single cycle paths. The simulation behavior of the path breaker is such that all access to a multi-cycle path at incorrect times gives an unknown result. The present invention's use of path breakers significantly improves static path analysis for digital circuits, and avoids errors inherent in static path analysis systems known in the prior art.